All microprocessors need to execute their first instructions, or “boot code,” after power-up or system reset from a non-volatile memory or other storage location which retains its data when power is off. Most current applications use a form of read-only memory (ROM) as their non-volatile memory to store the boot code, such as basic low-level operating system code (basic input/output system, BIOS). Such forms of ROM may be devices which can be written to a single time, such as Erasable Programmable Read Only Memory (EPROM), or devices which are in-system and re-programmable several times, such as traditional Electrically Erasable Programmable Read Only Memory (EEPROM), or a traditional flash device, often called NOR-Flash memory, which can erase entire blocks or sections of memory at once. These types of storage devices provide a simple Static Read Only Memory (SRAM) type interface, where an address is presented to the device and the data corresponding to the address is returned from the device after a short access delay time. This simple type of memory allows the boot code and low-level operating system code to be written to take full advantage of non-sequential execution (loops, if-then-else, branches, etc.) of code that is available on all processors.
As embedded processor systems more commonly rely on larger low-level operating systems to function, the storage requirements for the operating system code is outgrowing the capacity of traditional NOR-Flash and ROM non-volatile memory architectures. This has led to the increasing use of higher density NAND-based flash memories to contain the image of the operating system needed for an embedded processor system. NAND-flash memory devices are another type of non-volatile flash memory which have an advantage over the other types of non-volatile memory mentioned above: they store more data for the same silicon area. Thus, more non-volatile storage is available for the same cost and board area in comparison with the traditional non-volatile memory devices.
However, there are several difficulties associated with using NAND-Flash memory devices. NAND-Flash devices are controlled through commands instead of a simple SRAM interface, and thus must receive a specific command telling them to start to read data and then receive a command address to tell where that data should be fetched from. Furthermore, NAND-Flash is optimized for sequential (serial) access instead of the random access that is required for execution of software code from the memory; in comparison, NOR-Flash memory supports high-speed random access reads with parallel memory cell architecture. Thus, NAND-Flash devices have a restriction that, in order to get fast data read cycle times (e.g., 50 nanoseconds per byte), the data must be accessed sequentially. When a non-sequential piece of data is requested, there is a much larger access time (e.g., 50 microseconds) before the new data is available.
When accessing NAND-Flash for data, a command is first written to the NAND-Flash device to tell the device to enter a read mode, and then an address is written to the device to tell it where in the memory the processor wants to start to read data. Then, the NAND-Flash device drives a “busy” indicator signal until the desired page of data is available for reading. The time that this process takes is typically known as the “page read access time.” Once the NAND-Flash has dropped its busy indicator, the processor can begin to read data from the NAND-Flash in a sequential fashion (byte 0, byte 1, byte 2, etc.) for up to an entire device page size. The processor cannot make another random access to the NAND-Flash device unless it sends another command to the device and waits again for the page read access time to expire.
Thus, the interfacing requirements described above for NAND-Flash typically prevent this type of memory from being used for boot code/BIOS execution. However, some prior implementations have used NAND-Flash devices for such an application. For example, some NAND-Flash devices provide a strapping input pin called Power-On Read Enable (PRE) that automatically puts the NAND-Flash device into a sequential read mode. Since all accesses to NAND-Flash must be made in a sequential order, the software reset vector and initial program code must be “un-rolled” so that the order that the processor will fetch the code is the same order that the code is stored into the NAND-Flash device. This un-rolling can be complicated and requires in-depth knowledge of how the processor fetches code. Also, any branches or loops that may be present in the initial program code must be mapped into a linear sequence of operations in the external NAND-Flash device.
Another solution that has been used in some embedded processor designs is a circuit that automatically copies some amount of program code and/or data from the external NAND-Flash device into an on-chip SRAM. After this copy operation is completed, this circuit allows the processor to begin fetching its reset vector and boot code from the on-chip SRAM source, where random accesses are easily accomplished. The disadvantage of this method is that it requires that the chip design incorporate a fairly large amount of SRAM in order to have enough on-chip storage to contain all the code of the operating system. Additionally, this on-chip SRAM is typically not needed after boot time and wastes power and silicon die area after the initial boot-up is completed.
Accordingly, what is needed is a system and method that allows the execution of boot code directly from a serial memory device, such as a NAND-Flash device, and allows that memory device to store the operating system. The present invention addresses such a need.